Low current single chip oscillator timing circuit
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United States of America Patent
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Jan 6, 2015
Grant Date -
Mar 7, 2013
app pub date -
Aug 18, 2012
filing date -
Sep 7, 2011
priority date (Note) -
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Abstract
A low current single chip oscillator timing circuit which includes a dual mode capacitor circuit having a larger capacitance mode and a smaller capacitance mode having a fixed ratio. The timing circuit also includes an oscillator circuit that uses the dual mode capacitor circuit as a part of its time base wherein the large capacitance mode is operated with low power consumption and as needed includes a circuit that generates a reference pulse, wherein the short pulse and the reference pulse are compared and the result is used for correction to the oscillator frequency to create a feedback loop.
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