Digital data inversion flag generator circuit
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United States of America Patent
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Dec 23, 2014
Grant Date -
Mar 4, 2010
app pub date -
Aug 29, 2008
filing date -
Aug 29, 2008
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Abstract
An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.
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