Multi-port DRAM architecture for accessing different memory partitions
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United States of America Patent
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Dec 16, 2014
Grant Date -
Mar 25, 2010
app pub date -
Sep 22, 2008
filing date -
Sep 22, 2008
priority date (Note) -
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Abstract
Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.
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