Timer unit circuit having plurality of selectors and counter circuits that start counting in response to output of selectors
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United States of America Patent
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Dec 9, 2014
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N/A
app pub date -
Jan 4, 2012
filing date -
Nov 21, 2007
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Abstract
A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.
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