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• 15 United States
• 10 France
• 8 Japan
• 7 China
• 5 Korea
• 2 Other

Patent Owner(s)

Patent Owner	Address
GLAXOSMITHKLINE LLC	251 LITTLE FALLS DRIVE WILMINGTON DE 19808

International Classification(s)

• A61J:CONTAINERS SPECIALLY ADAPTED FOR MEDICAL OR PHARMA....
• B05C:APPARATUS FOR APPLYING LIQUIDS OR OTHER FLUENT MAT....
• B05D:PROCESSES FOR APPLYING LIQUIDS OR OTHER FLUENT MAT....
• B05B:SPRAYING APPARATUS; ATOMISING APPARATUS; NOZZLES
• B01J:CHEMICAL OR PHYSICAL PROCESSES, e.g. CATALYSIS, CO....
• A23G:COCOA; COCOA PRODUCTS, e.g. CHOCOLATE; SUBSTITUTES....
• A01C:PLANTING; SOWING; FERTILISING

• 2008 Application Filing Year
• A61J Class
• 127 Applications Filed
• 52 Patents Issued To-Date
• 40.95 % Issued To-Date

Inventor(s)

Inventor Name	Address	# of filed Patents	Total Citations
Fiesser, Frederick H	Collegeville, US	11	151
# of filed Patents : 11 Total Citations : 151

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Patent Citation Ranking

• 3 Citation Count
• A61J Class

• 6.76 % this patent is cited more than
• 11 Age

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Maintenance Fees

Fee	Large entity fee	small entity fee	micro entity fee	due date
11.5 Year Payment	$7400.00	$3700.00	$1850.00	May 18, 2026

Fee	Large entity fee	small entity fee	micro entity fee
Surcharge - 11.5 year - Late payment within 6 months	$160.00	$80.00	$40.00
Surcharge after expiration - Late payment is unavoidable	$700.00	$350.00	$175.00
Surcharge after expiration - Late payment is unintentional	$1,640.00	$820.00	$410.00

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
November 18, 2014	US,8887659,B2   US8887659B2	GRANTED PATENT AS SECOND PUBLICATION
April 01, 2010	US,20100080897,A1   US20100080897A1	FIRST PUBLISHED PATENT APPLICATION

Full Text

US Patent No: 9874925

Method and apparatus for a zero voltage processor sleep state

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Abstract

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Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

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Description

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Claims

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Claims data not available

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Legal Events

 

• AS2022
• MAFP2020
• I2018
• STCF2018
• P2016
• F2015

Date	Code	Event	Description
Jul 18, 2022	AS	ASSIGNMENT	free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061175/0176 Owner name: TAHOE RESEARCH, LTD., IRELAND Effective Date: Jul 18, 2022
Dec 07, 2020	MAFP	MAINTENANCE FEE PAYMENT	free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY year of fee payment: 4
Jan 23, 2018	I	Issuance
Jan 03, 2018	STCF	INFORMATION ON STATUS: PATENT GRANT	free format text: PATENTED CASE
Apr 07, 2016	P	Published
Dec 11, 2015	F	Filing