Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals
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United States of America Patent
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Dec 9, 2014
Grant Date -
Feb 27, 2014
app pub date -
Oct 31, 2013
filing date -
Oct 31, 2013
priority date (Note) -
Withdrawn
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Abstract
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section formed by connecting logic devices in series corresponding to a number of logic devices included in a clock signal path between a clock signal source and the latch circuit data input. The delay circuit also includes a second delay section having a delay time equal to an interconnect delay time corresponding to a wiring length of the clock signal path.
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