Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic
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United States of America Patent
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Oct 21, 2014
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app pub date -
Aug 30, 2010
filing date -
Aug 30, 2010
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Abstract
Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and jittery clock signal. The produced clock signal being provided as feedback to the digital frequency comparator and also acts as final dejitter smooth clock output with 50% duty cycle.
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