Frequency divider and PLL circuit
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United States of America Patent
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Oct 14, 2014
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app pub date -
Nov 8, 2012
filing date -
Nov 10, 2011
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Abstract
A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.
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