Memory device
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United States of America Patent
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Sep 16, 2014
Grant Date -
May 16, 2013
app pub date -
Nov 5, 2012
filing date -
Nov 16, 2011
priority date (Note) -
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Abstract
A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.
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