Importance

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Abstract

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate. Further, when the integrated circuit is in the power saving mode, the display controller streams the pixel data from the first memory to the display module at a second data rate that is lower than the first data rate, and the second memory is configured into a memory power-saving mode after the pre-fetching until the second memory is accessed for additional pixel data.

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First Claim