Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface
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United States of America Patent
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Aug 5, 2014
Grant Date -
May 20, 2010
app pub date -
Nov 18, 2008
filing date -
Nov 18, 2008
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Abstract
A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.
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