Display and automatic improvement of timing and area in a network-on-chip
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United States of America Patent
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Jul 29, 2014
Grant Date -
Dec 6, 2012
app pub date -
Jun 1, 2012
filing date -
Jun 2, 2011
priority date (Note) -
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Abstract
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.
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