Apparatus for executing programs for a first computer architecture on a computer of a second architecture
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United States of America Patent
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Jul 22, 2014
Grant Date -
Jun 7, 2012
app pub date -
Feb 13, 2012
filing date -
Jan 28, 1999
priority date (Note) -
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Abstract
A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.
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