Memory control device
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United States of America Patent
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Jul 22, 2014
Grant Date -
Apr 18, 2013
app pub date -
Apr 23, 2012
filing date -
Oct 13, 2011
priority date (Note) -
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Abstract
A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.
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