Multi-bit delta-sigma time digitizer circuit and calibration method thereof
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United States of America Patent
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Jul 15, 2014
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Aug 22, 2013
app pub date -
Feb 14, 2013
filing date -
Feb 16, 2012
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Abstract
According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.
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