Load reduction dual in-line memory module (LRDIMM) and method for programming the same
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United States of America Patent
Stats
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May 27, 2014
Grant Date -
Sep 12, 2013
app pub date -
Apr 30, 2013
filing date -
Sep 15, 2008
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual inline memory module (RDIMM) in which control signals are synchronusly buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.
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Cited Art Landscape
Patent Citation Ranking
- 66 Citation Count
- G06F Class
- 89.24 % this patent is cited more than
- 11 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Nov 27, 2025 |
