Stacked seminconductor package
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United States of America Patent
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May 20, 2014
Issued Date -
N/A
app pub date -
May 11, 2011
filing date -
May 10, 2010
priority date (Note) -
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Abstract
Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate including at least one contact pad; an external chip laminate which includes a plurality of semiconductor chips mounted on the substrate, and which is stacked in multi-steps such that the ends at one side of the plurality of semiconductor chips alternately protrude in opposite directions to expose bonding pads which are formed on the up-face surface; at least one internal chip which is disposed in a mounting space formed between the external chip laminate and substrate so as to be electrically connected to the substrate; and a conductive wire electrically connecting the bonding pad of the semiconductor chip and the contact pad of the substrate.
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