Dynamic buffer management in a NAND memory controller to minimize age related performance degradation due to error correction
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United States of America Patent
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May 13, 2014
Grant Date -
Dec 1, 2011
app pub date -
Jun 1, 2010
filing date -
Jun 1, 2010
priority date (Note) -
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Abstract
An output buffer circuit for a non-volatile memory comprises an error check circuit, an error correction circuit, a switch circuit, and three storage circuits. The error check circuit receives the plurality of data bits and the plurality of ECC bits from the non-volatile memory to determine if the plurality of data bits need to be corrected and generates a correction signal. The error correction circuit receives the plurality of data bits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. A switch enables the output buffer circuit to concurrently performs operations of error check, error correction, and transfer of data bits out of the output buffer circuit on three distinct pluralities of data bits. The switch allows reallocation of storage circuits to different operations without any data transfer.
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