Scenario driven concurrency bugs: model and check

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United States of America Patent

PATENT NO 8707272
APP PUB NO 20120174074A1
SERIAL NO

13343361

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A computer implemented testing methodology employing a scenario-driven modeling of specific instances of bug patterns that commonly occur in concurrent programs which encodes these instances in an SMT-based symbolic analysis. Such modeling and encoding advantageously allow the symbolic analysis framework to focus on real bugs, thereby allowing effective utilization of resources. Experimentation determined a number of previously unknown bugs in public benchmarks and advantageously scenario-specific modeling and encoding improves the scalability of symbolic technique and, therefore, improves overall quality of concurrency testing.

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NEC CORPORATION7-1 SHIBA 5-CHOME MINATO-KU TOKYO 108-8001

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Inventor Name Address # of filed Patents Total Citations
Ganai, Malay Princeton, US 21 542

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