Integrated circuit routing with compaction
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United States of America Patent
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Apr 22, 2014
Grant Date -
Apr 25, 2013
app pub date -
Dec 11, 2012
filing date -
Jun 24, 2005
priority date (Note) -
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Abstract
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.
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