Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC
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United States of America Patent
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Mar 18, 2014
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N/A
app pub date -
Oct 11, 2012
filing date -
Oct 11, 2012
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Abstract
A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.
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