Circuits and methods for clock generation using a flying-adder divider inside and optionally outside a phase locked loop
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United States of America Patent
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Mar 4, 2014
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app pub date -
Nov 14, 2012
filing date -
Nov 14, 2012
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Abstract
A phase locked loop including a flying-adder divider circuit configured to receive phases of a periodic signal from a frequency generator and output a feedback signal to a phase detector, and a method of generating a periodic signal using such a flying-adder circuit, are disclosed. The flying-adder divider circuit generally includes a flying-adder and one or two divide-by-N dividers. The flying-adder receives K phases of the periodic signal, where K is an integer of at least 2, and generates a divided periodic signal from the K phases. The phase locked loop may include flying-adder divider circuits inside and/or outside the loop.
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