Cache memory architecture having reduced tag memory size and method of operation thereof
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United States of America Patent
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Feb 25, 2014
Grant Date -
Apr 8, 2010
app pub date -
Oct 3, 2008
filing date -
Oct 3, 2008
priority date (Note) -
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Abstract
A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address.
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