Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software
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United States of America Patent
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Feb 18, 2014
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N/A
app pub date -
Dec 16, 2010
filing date -
Jun 25, 2009
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Abstract
In one embodiment of the invention, a design verifier is disclosed including a model extractor and a bounded model checker having an arithmetic satisfiability solver. The arithmetic satisfiability solver searches for a solution in the form of a numeric assignment of numbers to variables that satisfies each and every one of the one or more numeric formulas. Conflict in the search, results in the deduction of one or more new numeric formulas that serve to guide the search toward a solution. If the search finds a numeric assignment that satisfies each and every one of the one or more numeric formulas, it indicates that a functional property of the system is violated.
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