Digital clock regenerator
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United States of America Patent
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Jan 14, 2014
Grant Date -
Nov 22, 2012
app pub date -
Feb 17, 2010
filing date -
Feb 17, 2010
priority date (Note) -
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Abstract
A sampling unit (110) receives an input clock signal (CLKin) having a varying period time, and samples the input clock signal (CLKin) based on a sampling clock signal (CLKsmpl) that has a frequency being substantially higher than an average frequency of the input clock signal (CLKin). The sampling unit (110) produces a respective period length value (PL) for each period of the input clock signal (CLKin). An averaging unit (120) receives a number of period length values (PL) from the sampling unit (110), and based thereon produces an average period length value (PLavg) representing an average period time for the input clock signal (CLKin) over an averaging interval including a number of periods equivalent to said number of period length values (PL). An output unit (151) produces a stabilized output clock signal (CLKout) based on the average period length value (PLavg) and the sampling clock signal (CLKsmpl).
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