Spacer protection and electrical connection for array device
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United States of America Patent
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Jan 7, 2014
Grant Date -
Sep 22, 2011
app pub date -
Mar 22, 2010
filing date -
Mar 22, 2010
priority date (Note) -
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Abstract
The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
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