Reference current source circuit including added bias voltage generator circuit
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United States of America Patent
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Dec 24, 2013
Grant Date -
Feb 2, 2012
app pub date -
Jul 28, 2011
filing date -
Jul 30, 2010
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Abstract
A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER | TOKYO 105-0004 |
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Hirose, Tetsuya | Hyogo, JP | 45 | 460 |
Osaki, Yuji | Hyogo, JP | 15 | 80 |
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