Method and system for verification of electrical circuit designs at process, voltage, and temperature corners
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United States of America Patent
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Dec 17, 2013
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Nov 7, 2012
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Nov 8, 2011
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Abstract
A method for finding the process, voltage, temperature, parasitics, and power settings (PVTPP) corner at which an electrical circuit design has the worst-case optimum simulated output performance. The method uses a global optimization process in a series of iterations that aim to uncover the PVTPP corner at which the ECD has the worst-case output value. By using the present method, a designer does not have to simulate the ECD at each and every PVTPP corner, which can same considerable time or compute effort. Examples using Model-Building Optimization are provided.
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