Semiconductor device
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United States of America Patent
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Dec 10, 2013
Grant Date -
Jun 14, 2012
app pub date -
Feb 17, 2012
filing date -
Oct 23, 2009
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

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- 15 United States
- 10 France
- 8 Japan
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- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
PANNOVA SEMIC LLC | 3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Akamatsu, Susumu | Osaka, JP | 23 | 266 |
Fujimoto, Hiromasa | Toyama, JP | 30 | 194 |
Itou, Satoru | Hyogo, JP | 10 | 52 |
Kutsunai, Toshie | Osaka, JP | 28 | 280 |
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