Frequency-locked synthesizer with low power consumption and related system and method
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United States of America Patent
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Dec 3, 2013
Grant Date -
Aug 15, 2013
app pub date -
Feb 13, 2012
filing date -
Feb 13, 2012
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Abstract
An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable.
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