Compressed instruction format for use in a VLIW processor
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 12, 2013
Grant Date -
Sep 16, 2004
app pub date -
Jan 22, 2004
filing date -
May 15, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully