WAFER-LEVEL PROCESS FOR FABRICATING PHOTOELECTRIC MODULES
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United States of America Patent
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Nov 12, 2013
Grant Date -
Nov 21, 2013
app pub date -
May 15, 2012
filing date -
May 15, 2012
priority date (Note) -
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Abstract
A wafer-level process for fabricating a plurality of photoelectric modules is provided. The wafer-level process includes at least following procedures. Firstly, a wafer including a plurality of chips arranged in an array is provided. Next, a plurality of photoelectric devices are mounted on the chips. Next, a cover plate including a plurality of covering units arranged in an array is provided. Next, a plurality of light guiding mediums are formed over the cover plate. Next, the cover plate is bonded with the wafer by an adhesive, wherein each of the covering units covers and bonds with one of the chips, and the light guiding mediums are sandwiched between the cover plate and the wafer. Then, the wafer and the cover plate are diced to obtain the plurality of photoelectric modules.
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