Memory arrangement for multi-processor systems including a memory queue
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United States of America Patent
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Oct 15, 2013
Grant Date -
Jun 12, 2008
app pub date -
Dec 28, 2007
filing date -
Jun 30, 2005
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Abstract
A hardware memory architecture or arrangement suited for multi-processor systems or arrays is disclosed. In one aspect, the memory arrangement includes at least one memory queue between a functional unit (e.g., computation unit) and at least one memory device, which the functional unit accesses (for write and/or read access).
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