Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping

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United States of America

PATENT NO 8555223
SERIAL NO

13445832

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Abstract

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Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

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Patent Owner(s)

  • CADENCE DESIGN SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baudhuin, Joshua Portland, US 4 23
Rosek, Timothy Gibsonia, US 5 36
Xu, Hui Wexford, US 440 2426
Yu, Henry Palo Alto, US 70 531

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