Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 17, 2013
Grant Date -
Jul 5, 2012
app pub date -
Mar 15, 2012
filing date -
Jul 27, 2009
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully