NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers
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United States of America Patent
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Sep 10, 2013
Grant Date -
Dec 1, 2011
app pub date -
May 26, 2011
filing date -
May 28, 2010
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Abstract
A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.
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