Pipelined analog-to-digital converter and its single redundancy bit digital correction technique
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United States of America Patent
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Sep 10, 2013
Grant Date -
Nov 17, 2011
app pub date -
Jun 21, 2010
filing date -
Jun 22, 2009
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Abstract
A pipeline A/D converter and its single redundancy bit digital correction are provided. The single redundancy bit digital correction includes the following steps: substages except for the last one quantizes input voltage, calculates the residual voltage, which is amplified and shifted to the middle part of the reference voltage range, and outputs to the following substage until the last one, which only quantizes the input voltage; the code and offset code of each substage corresponding to the quantized thermometer code are calculated; the offset codes of all stages are added by weight to get total offset code; and codes of all substages are added by weight, to which the total offset code is added. The comparator offset error is corrected to obtain an output code which identifies the negative or positive overflow of input signals. The A/D converter adopting the above digital correction is provided.
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