Method and structure for producing high performance linear algebra routines using composite blocking based on L1 cache size

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United States of America Patent

PATENT NO 8527571
APP PUB NO 20090106343A1
SERIAL NO

12341718

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Abstract

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A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK NEW YORK 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gunnels, John A Mt. Kisco, US 78 1682
Gustavson, Fred Gehrung Briarcliff Manor, US 26 366

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