Critical path monitor for an integrated circuit and method of operation thereof
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United States of America Patent
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Jul 30, 2013
Grant Date -
Nov 12, 2009
app pub date -
Oct 8, 2008
filing date -
May 7, 2008
priority date (Note) -
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status (Latency Note)
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Abstract
A path monitor, a method of monitoring a path, an integrated circuit and a library of standard logic elements. In one embodiment, the path monitor includes: (1) a delay element having an input couplable to an input of a clocked flip-flop associated with a path to be monitored and configured to provide a predetermined delay and (2) a clocked exclusive OR gate having a clock input, a first input coupled to an output of the delay element, a second input couplable to the output of the clocked flip-flop and an output at which the clocked exclusive OR gate is configured to respond to a clock signal to provide an error signal only when logic levels of the first input and the second input differ.
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