Method of cavity forming on a buried resistor layer using a fusion bonding process
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United States of America Patent
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Jul 23, 2013
Grant Date -
Oct 11, 2012
app pub date -
Apr 8, 2011
filing date -
Apr 8, 2011
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Abstract
A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.
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