Standard cells having transistors annotated for gate-length biasing
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United States of America Patent
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Jul 16, 2013
Grant Date -
Jul 1, 2010
app pub date -
Mar 4, 2010
filing date -
May 6, 2005
priority date (Note) -
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Abstract
A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.
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