Method for forming an integrated circuit level by sequential tridimensional integration
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United States of America Patent
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Jul 16, 2013
Grant Date -
Dec 9, 2010
app pub date -
Jun 4, 2010
filing date -
Jun 5, 2009
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Abstract
A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
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