Memory array and method of operating the same
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United States of America Patent
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Jul 9, 2013
Grant Date -
Jan 24, 2013
app pub date -
Aug 10, 2011
filing date -
Jul 27, 2011
priority date (Note) -
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Abstract
A memory device comprises at least one memory array on a semiconductor substrate. Each said memory array comprises a page control line and a plurality of pages, each said page is arranged in a row comprising a plurality of bytes which couple to a page control transistor with its drain terminal connected to the page control line. Each said byte includes at least one memory cell. Said memory array further comprises a plurality of source control devices which are configured to provide either predetermined biases or floating potentials to source lines, each said source line couples to all the bytes on the same byte segment of the memory array. Read, erase, and program methods are provided to operate said memory devices in byte addressable fashion.
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