Vertical complementary FET
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United States of America Patent
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Jul 2, 2013
Grant Date -
Sep 13, 2012
app pub date -
Mar 6, 2012
filing date -
Mar 9, 2011
priority date (Note) -
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Abstract
A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced.
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