Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
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United States of America Patent
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Jun 11, 2013
Grant Date -
Jun 30, 2011
app pub date -
Dec 23, 2010
filing date -
Dec 29, 2009
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Abstract
Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.
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