ESD protection devices for SOI integrated circuit and manufacturing method thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 11, 2013
Grant Date -
May 10, 2012
app pub date -
Dec 16, 2010
filing date -
Nov 4, 2010
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully