Spacer and process to enhance the strain in the channel with stress liner

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United States of America Patent

PATENT NO 8461009
APP PUB NO 20070202654A1
SERIAL NO

11307928

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Abstract

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Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

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Patent Owner(s)

Patent OwnerAddress
CHARTERED SEMICONDUCTOR MANUFACTURING LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738046

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ajmera, Atul C Wappingers Falls, US 17 342
Baiocco, Christopher V Newburgh, US 17 125
Chen, Xiangdong Poughquag, US 216 2796
Gao, Wenzhi Beacon, US 11 136
Teh, Young Way Singapore, MY 28 419

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