Method of wafer-level fabrication of MEMS devices
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United States of America Patent
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May 21, 2013
Grant Date -
Jun 16, 2011
app pub date -
Dec 14, 2010
filing date -
Dec 16, 2009
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Abstract
The present disclosure relates to a method of fabricating a micromachined CMOS-MEMS integrated device as well as the devices/apparatus resulting from the method. In the disclosed method, the anisotropic etching (e.g., DRIE) for isolation trench formation on a MEMS element is performed on the back side of a silicon wafer, thereby avoiding the trench sidewall contamination and the screen effect of the isolation beams in a plasma etching process. In an embodiment, a layered wafer including a substrate and a composite thin film thereon is subjected to at least one (optionally at least two) back side anisotropic etching step to form an isolation trench (and optionally a substrate membrane). The method overcomes drawbacks of other microfabrication processes, including isolation trench sidewall contamination.
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