Integrated circuit having a scan chain and testing method for a chip
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United States of America Patent
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May 7, 2013
Grant Date -
May 17, 2012
app pub date -
Jan 26, 2012
filing date -
Oct 12, 2009
priority date (Note) -
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Abstract
An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.
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