Multi-stack memory device
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United States of America Patent
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May 7, 2013
Grant Date -
Jun 12, 2008
app pub date -
Oct 30, 2007
filing date -
Dec 12, 2006
priority date (Note) -
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Abstract
Provided is a multi-stack memory device that includes a storage unit group including a plurality of storage units that are vertically stacked and form a plurality of storage unit rows, and a plurality of transistors connected to the storage unit group, wherein the transistors that are connected to the storage units which are included in at least two rows of the plurality of the storage unit rows and are connected by a common wire. The common wire may be a gate line or a bit line.
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